1. Field of the Invention
The present invention relates to a programmable logic device and, more particularly, to a field programmable gate array where desired logics to be realized are programmable by a user in accordance with individual application. Further particularly, the invention relates to improvements in a signal transmission circuit to reduce a signal propagation delay in a field programmable gate array.
2. Description of the Related Art
Out of logic integrated circuits designed to realize logics that satisfy the specifications required by users, there is known a gate array. In such a gate array, transistors are arrayed regularly, and interconnection lines programmed by a mask in accordance with each users' required specification, to interconnect the transistors (gates) to thereby realize the desired logics. In a gate array, however, since logics are programmed by means of mask interconnection lines, it is impossible to rearrange the logics once programmed. Gate arrays of this type are intended to be mass-produced to a certain extent. When a user forms a logic circuit as a trial or needs merely a small amount of logic circuits, there is used a programmable logic device termed "field programmable logic array (FPGA)". This field programmable logic array incorporates memory cells (SRAM cells), which are programmed to realize a desired internal circuit specification (including internal logic construction and line connection).
FIG. 19 schematically shows a whole constitution of a conventional field programmable gate array. Referring to input/output blocks IOB are disposed along peripheral portions of a chip, and programmable logic circuit blocks PLB are disposed to form a matrix of rows and columns in the inner region of these input/output blocks IOB. The input/output blocks IOB correspond respectively to data input/output terminals (not shown), and the internal constructions thereof are programmable. Also the internal logic constructions of the programmable logic circuit blocks PLB are programmable as well. Exemplary programming thereof will be described later.
The region between the programmable logic circuit blocks PLB, and also the region between the input/output blocks IOB and the programmable logic circuit blocks PLB, are each utilized as interconnection regions IR. As will be explained later, interconnection lines for interconnecting circuit blocks are disposed in the interconnection line region IR. In this interconnection line region IR, switching transistors are arranged corresponding to intersections of the interconnection lines. And connections of the interconnection lines IL between input/output blocks IOB and programmable logic circuit blocks PLB, and also signal propagation paths therebetween, are established by setting the on/off states of switching transistors in accordance with storage data in the memory cells. A memory cell is provided in each of the input/output blocks IOB and the programmable logic circuit blocks PLB, and the functions of circuit blocks are programmed by externally writing storage data in the memory cells.
As will be described later, the memory cells are so arranged as to form a matrix of rows and columns in the interconnection line region. A data shift register DR and an address shift register AR are provided for writing data in the memory cells. The data shift register DR sequentially shifts the data obtained from a not-shown data input terminal and stores the data to be written in the memory cells of one row. The address shift register AR generates a signal to select one row of the memory cells in response to a clock signal obtained from a not-shown clock buffer. Consequently, the stored data in the data shift register are written in the memory cells of one row simultaneously.
FIG. 20 shows a configuration of the interconnection line regions shown in FIG. 19. In FIG. 20, interconnection line groups ILG are disposed in the interconnection line region IR among a plurality (six in FIG. 20) of programmable logic circuit blocks PLB arranged in rows and columns. Each interconnection line group ILG includes a plurality of interconnection lines ILA and ILB disposed respectively in a row direction (horizontal direction in FIG. 20) and a column direction (vertical direction in the FIG. 20). Switch matrixes SM are provided at the intersections of the interconnection line groups ILG (interconnection lines ILA and ILB). Each switch matrix SM includes a plurality of switching transistors as will be described later, and interconnection of the interconnection lines is established by programming the on/off states of such switching transistors, and also connection between the programmable logic block PLB and the interconnection lines ILA or ILB is established by the same programming.
FIG. 21 shows a specific structure of the switch matrix in FIG. 20. In FIG. 21, there is illustrated an arrangement of switching elements provided corresponding to the intersections of four horizonwise interconnection lines ILA0-ILA4 and four verticalwise interconnection lines ILB0-ILB3. Memory cells MCB shown in FIG. 21 are utilized for interconnecting programmable logic circuit blocks PLB and interconnection lines. FIG. 21 represents an exemplary mode of programming the on/off states of switching elements ST0-ST3 provided at the intersections of the interconnection lines ILB0-ILB3 and the input/output interconnection lines IOL connected to the input/output port of the programmable logic block PLB.
The memory cells MCA are so arrayed as to form a matrix, and one row of the memory cells MCB and one column of the memory cells MCB are disposed adjacent to each side of the matrix of such memory cells MCA. As a result, the memory cells MCA and MCB are arrayed in rows and columns to constitute a memory matrix. Word lines WL (WL0-WL5) are disposed corresponding to the rows of the memory matrix, and data lines (bit lines) BL (BL0-BL4) are disposed corresponding to the columns of the memory matrix. Switching elements SW are disposed correspondingly to the memory cells MCA. The on/off states of the switching elements SW are determined in accordance with storage data of the individual memory cells MCA corresponding thereto respectively.
At the time of writing data in the memory cells MCA and MCB, one word line WL (out of WL0-WL5) is placed in a selected state, and then one row of the memory cells MCA or MCB are selected. Subsequently the data to be written in the selected memory cells MCA and MCB of one row are transmitted to the data lines BL0-BL4, and the data on the data line corresponding to such memory cells of one row are written therein. Thus, interconnections of the programmable logic blocks, i.e., signal propagation paths, are established by writing predetermined data in the memory cells MCA and MCB.
FIG. 22 illustrates an exemplary structure of the memory cell shown in FIG. 21. In FIG. 22, the memory cell MC (MCA or MCB) includes an access transistor NA of an n-channel MOS transistor (insulated gate type field effect transistor) which conducts in response to a signal potential on the word line WL to connect an internal node NDA to the data line BL, a first inverter IV1 for inverting and amplifying the signal potential on the internal node NDA and transmitting the amplified potential to an internal node NDB, and a second inverter IV2 for inverting and amplifying the signal potential on the internal node NDB and transmitting the amplified potential to the internal node NDA. Such inverters IV1 and IV2 constitute a latch circuit.
The first inverter IV1 includes a p-channel MOS transistor PM1 which is provided between a power supply node VDD and the internal node NDB and receives at its gate the signal potential on the internal node NDA, and an n-channel MOS transistor NM1 which is provided between the internal node NDB and a ground potential node GND and receives at its gate the signal potential on the internal node NDA. The second inverter IV2 includes a p-channel MOS transistor PM2 which is provided between the power supply node VDD and the internal node ND1 and receives at its gate the signal potential on the internal node ND2, and an n-channel MOS transistor NM2 which is provided between the internal node NDA and the ground potential node GND and receives at its gate the signal potential on the internal node NDB.
A word line selection signal from the address shift register AR (FIG. 19) is transmitted to the word line WL. A data signal from the data shift register DR (FIG. 19) is transmitted to the data line BL. The data shift register DR holds the data of one-row memory cell, and the address shift register AR drives the word lines WL sequentially into a selected state. When the signal potential on the word line WL has become a high ("H") level indicative of a selected state, the access transistor NA in the memory cell MC is switched on so that the internal node NDA is connected to the data line BL. Consequently the signal potential on the data line BL is transmitted as program data to the internal node NDA and then is latched by the inverters IV1 and IV2. After completion of writing the data, the potential on the word line WL is turned to a low ("L") level, so that the access transistor NA is switched off, and the signal potential on the internal node NDA is held by the inverters IV1 and IV2 as long as a predetermined potential is applied to the power supply node VDD and the ground potential node GND. The signal potential on the internal node NDB is applied to a gate terminal (control electrode) of the corresponding switching element SW or ST to thereby determine the on/off state of the corresponding switching element.
FIG. 23 shows an exemplary mode of programming a signal propagation path between two programmable logic circuit blocks. In FIG. 23, data "0" (corresponding to a low-level potential) is stored in memory cells M01-M02 (in the node NDB of FIG. 22), and data "1" (corresponding to a high-level potential) is written in the remaining memory cells M11-M15. Switching elements N01-N02 are turned off, while the remaining switching elements N11-N15 are turned on. The switching element N11 interconnects interconnection lines IL0 and IL1; switching elements N12 . . . N13 interconnect interconnection lines IL1 and IL2; and switching elements N14 . . . N15 interconnect interconnection lines IL2 and IL3. Therefore, the programmable logic circuit block PLBA is connected via the interconnection lines IL0, IL1, IL2 and IL3 to the programmable logic circuit block PLBB. The signal propagation path between the two programmable logic circuit blocks PLBA and PLBB is established by the storage data in the memory cells MC (M01, M02, M11-M15). The propagation path of the signal outputted from the logic circuit block PLBA can be changed by rewriting the storage data in the memory cells MC. That is, an interconnection network is reconstructible by the storage data in the memory cells MC, and in determining the specification of a trial product or the like, it becomes possible to determine an appropriate internal specification for attaining optimal performance characteristics.
FIG. 24 shows an equivalent circuit of the signal propagation path between the two logic circuit blocks in FIG. 23. In FIG. 24, switching elements N11-N1n are connected in series between the two logic circuit blocks PLBA and PLBB. A parasitic capacitance CL0 is associated to the interconnection line between the logic circuit block PLBA and the switching element N11. Similarly, parasitic capacitances CL1-CL(n-1) are present respectively on the signal interconnection lines between the switching elements, and a parasitic capacitance CLn is associated to the signal line between the switching element N1n and the logic circuit block PLBB. Memory cells M11-M1n are provided in correspondence to the switching elements N11-N1n respectively. A potential equal in level to the supply potential VDD is held in the internal node NDB of such memory cells M11-M1n. Here, the power supply node and the supply potential fed thereto will be described below with the same reference symbols.
An output buffer including an inverter circuit is provided in an output stage of the logic circuit block PLBA, and an input buffer including an inverter circuit is provided in the logic circuit block PLBB. When a signal is propagated from the logic circuit block PLBA to the logic circuit block PLBB, the signal propagation is delayed due to the internal resistances (on-resistances) of the switching elements N11-N1n and the parasitic capacitances CL0-C1n respectively on the signal interconnection lines, whereby it is rendered impossible to perform high-speed transmission of the signal to the logic circuit block PLBB. A voltage equal in level to the power supply potential VDD is transmitted to the control electrodes of the switching elements N11-N1n from the corresponding memory cells M11-M1n respectively. Each of the switching elements N11-N1n is comprised of an n-channel MOS transistor. Each n-channel MOS transistor is capable of transmitting, from a source to a drain, a voltage level (VDD-Vth) which is obtained by subtracting a threshold voltage Vth from the voltage applied to its gate. Therefore, in the arrangement of FIG. 24, the high ("H") level at the nodes ND1-NDn is equal to the voltage level lower by the threshold voltage Vth than the maximum power supply potential VDD, so that the high level of a signal can not full swing up to the power supply voltage VDD. Consequently, the voltage of the CMOS level can not be transmitted to the input buffer of the logic circuit block PLBB, and the p-channel MOS transistor in the input buffer can not be completely turned off, whereby there arises a problem that a through current flows therethrough to eventually bring about an increase of the current consumption.
As the distance from the logic circuit block PLBA becomes longer, the resistance R (derived from the switching element and the interconnection line) and the capacitance C (including the parasitic capacitance) in the signal line increase to consequently cause an RC delay, which raises a problem that the signal can not be changed fast and the rounding of the waveform is rendered great.
FIG. 25 graphically shows the result of simulating the signal waveform changes the node ND0 (output of the logic circuit block PLBA) and the node ND3 (input of the other logic circuit block PLBB) in an exemplary case where three switching elements (n=3) is connected in series to one another and the two logic circuit blocks PLBA and PLBB are mutually connected. In FIG. 25, the ordinate represents a voltage (V), while the abscissa represents a time (ns). As obvious from this graph, when a signal of 3.0 V (=VDD) is outputted from the logic circuit block PLBA, a high-level signal having an amplitude of 1.6 or so is transmitted to the input of the logic circuit block PLBB, and the waveform of the signal transmitted to the logic circuit block PLBB is greatly rounded. In particular, such rounding of the signal waveform is more conspicuous at a rise of the signal from a low level to a high level than at a fall thereof from a high level to a low level. This phenomenon is based on the fact that the capacitance is discharged fast, whereas the potential rise at the signal node by charging of the capacitance is relatively slow. When the power supply potential VDD is 3.0 V, as shown in FIG. 25, a high-level signal of 1.6 V or so is propagated to the input of the logic circuit block PLBB, whereby the p-channel MOS transistor of the input buffer in the logic circuit block PLBB is not fully turned off, and a through current comes to flow to cause a current consumption. In addition, it becomes difficult to make an accurate discrimination between a high level and a low level in the input buffer, hence bringing about a failure in a correct operation. There occurs another disadvantage that a fast operation cannot be ensured either due to the delay in the signal propagation.
As described above, in the conventional field programmable gate array having an advantage that signal propagation paths can be established merely by programming the storage data in SRAM (static random access memory) cells to thereby program the interconnection paths in an interconnection line network, there exists a problem that the delay in the signal propagation is rendered great in the interconnection lines where a multiplicity of switching elements are connected in series between two logic circuit blocks, and the signal propagation cannot be performed fast in the interconnection line network. Further the threshold voltage loss in the n-channel MOS transistors serving as switching elements increases relative to the logic level of a signal, in accordance with a reduction of the power supply potential VDD to 3 V or 1.5 V under the condition that the threshold voltage remains unchanged. In order to prevent the harmful influence resulting from drop of the threshold voltage in the switching element, it is necessary to equip a buffer circuit and so in the signal propagation path to boost the signal level on the signal line, hence raising another problem of an increase of the chip area.